Complementary Metal Oxide Semiconductor (“CMOS”) Field Effect Transistors (“FETs”) are employed in almost every electronic circuit application, such as signal processing, computing, and wireless communications. One known type of FET is a Silicon-On-Insulator (“SOI”) FET. An SOI transistor with a very thin SOI body thickness and optional light halo doping has very good short channel control. More information of such SOI transistors is available in the references B. Doris et al., “Extreme scaling with ultra-thin Si channel MOSFETs” (IEDM Technical Digest, 2002); B. Doris et al., “Device design considerations for ultra-thin SOI MOSFETs” (IEDM Technical Digest, 2003); and D. V. Singh et al., “Stress memorization in high-performance FDSOI devices with ultra-thin silicon channels and 25 nm gate lengths” (IEDM Technical Digest, 2005), all of which are herein incorporated by reference.
While thin SOI transistors allow very good short channel control, an undoped or lightly-doped Extremely Thin Silicon-On-Insulator (“ETSOI”) transistor with a conventional heavily-doped polysilicon gate has a very low threshold voltage (VT), which leads to a very high transistor off current (IOFF). An alternative is to use a high-K dielectric and metal gate stack. The resulting ETSOI transistor has a targeted threshold voltage (VT), which leads to a lower transistor off current (IOFF) than the conventional heavily-doped polysilicon gate transistor due to improved sub-threshold slope (SSSAT). The high-K dielectric and metal gate stack also increases the gate capacitance (CG), which leads to a higher transistor on current (IDSAT). However, an ETSOI transistor with a high-K dielectric and gate stack without proper spacers suffers from the growth of an underlayer of oxide that lowers the gate capacitance. Furthermore, any thin-body SOI transistor like an ETSOI transistor needs an epitaxial raised source/drain to obtain a low transistor series resistance. However, the formation of a raised source/drain also requires the use of spacers for selective epitaxial growth, which leads to silicon loss during reactive-ion etching (“RIE”) of the spacer.
FIG. 10 shows a known FET with a high-K dielectric, metal gate, and oxide-nitride-oxide spacers. As shown, this transistor has a high-K gate dielectric 2310, a gate electrode 2312 that is polysilicon, poly-SiGe, or metal, an oxide liner 2328, a nitride liner 2330, and oxide sidewall spacers 2334 and 2336 that are formed by oxide RIE that stops on the nitride liner 2330. The oxide liner 2328 that is in contact with the high-K gate dielectric 2310 leads to the growth of an underlayer of oxide beneath the high-K oxide. This underlayer of oxide (or “underoxide”) lowers the gate capacitance, which is not desirable.
Another known FET structure has a raised source/drain, high-K dielectric, metal gate, and oxide-nitride spacers. This transistor has an L-shaped oxide spacer, a nitride spacer, and a high-K gate oxide. The oxide spacer is in contact with the high-K gate oxide, which leads to underoxide growth. This lowers the gate capacitance, which is not desirable.
Yet another known FET structure has L-shaped nitride spacers and a raised source/drain. For this FET structure, photolithography and a hot phosphoric acid wet etch are used to form the L-shaped nitride spacers, and subsequent epitaxial growth is used to form the raised source/drain. However, this process is not self-aligned. This causes the L-shaped nitride spacers to be asymmetric, with about 10 nm of asymmetry because of overlay errors that cannot be controlled to better than 10 nm with current processes. With this process, if nitride RIE was instead used to form symmetric, self-aligned sidewall spacers, the nitride RIE would not stop on the underlying silicon. Thus, the result would be silicon loss, which leads to a high series resistance and a low on current. Such silicon loss cannot occur in the fabrication of an ETSOI transistor because of the extreme thinness of the silicon layer.